a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a process of patterning a lamination of a silicon film and a metal film formed thereon.
b) Description of the Related Art
Low resistance of gate electrodes is becoming the requisite for the recent high performance of MOS transistors. Low resistance techniques, especially using a lamination of a silicon film and a metal film as a gate electrode, have drawn much attention.
Technique of patterning a laminated structure of tungsten (W) and TiN is disclosed in JP-A-4-219929. With this technique, the upper W layer is first etched with F containing gas by using as an etching mask a resist pattern formed on the W layer. Thereafter, the lower TiN layer is etched with Cl.sub.2 or Br containing gas. After the TiN layer is etched, the resist pattern is removed to form a patterned lamination structure of W and TiN films. With this technique, a gate electrode structure of a lamination of W/TiN/Si can be formed.
When a lamination structure of gate electrode layers is etched to leave the gate electrode structure, the gate insulating layer is exposed on both sides of the gate electrode structure. In order not to damage a silicon layer under the gate insulating layer, it is desired to automatically stop etching when the gate insulating layer is exposed. To this end, it is necessary to set a high etching selection ratio of the lamination structure of gate electrode layers to the gate insulating layer. The etching conditions disclosed in JP-A-4-219929, however, use an insufficient etching selection ratio, and the silicon layer under the gate insulating layer is likely to be damaged.